1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device which operates in synchronization with an externally applied clock signal having a predetermined cycle, and in particular to a structure of a signal input portion of the synchronous semiconductor memory device operable in a low power consumption mode.
2. Description of the Background Art
A microprocessor internally has a cache memory of a small storage capacity. In order to improve a system performance by reducing a wait time of the microprocessor at the time of cache miss, such a structure may be employed that the microprocessor is externally provided with a memory having a relatively large storage capacity, which is used as a secondary cache. The memory used as the secondary cache operates in synchronization with an external clock signal such as a system clock. Since it is not necessary to take a margin with respect to skew of a signal into consideration, and a deciding timing of input/output data is determined by the clock signal, fast input and output of data are allowed, and cache miss penalty can be suppressed.
FIG. 1 schematically shows a whole structure of a conventional synchronous semiconductor memory device operating in synchronization with a clock signal. The synchronous semiconductor memory device shown in FIG. 1 includes an SRAM (Static Random Access Memory) array 1 having a storage capacity of 32k.32-bits. One word consists of 32 bits. SRAM cells included in array 1 have the same structure as memory cells included in a conventional SRAM, and are formed of flip-flops.
The synchronous semiconductor memory device further includes input circuits 2a-2r which receive externally applied signals and produce internal signals. Input circuit 2a receives an externally applied address signal. Input circuit 2b receives a burst mode control signal MODE which determines a mode of changing the addresses in a burst mode as will be described later. In the burst mode, when one address is designated, data of memory cells at four addresses are continuously read or written.
Input circuit 2c receives a snooze mode signal /ZZ. In the snooze mode, the semiconductor memory device stops its operation, so that the power consumption of the semiconductor memory device is minimized.
Input circuit 2d receives a burst mode advance signal /ADV. When burst mode advance signal /ADV is active, address signals are automatically generated in the semiconductor memory device.
Input circuit 2e receives an externally applied clock signal CLK. Internal clock signal CLK produced by input circuit 2e determines the timing of taking in the external signals and the timing of inputting and outputting data. At the time of rising of internal clock signal CLK, the externally applied address signal is taken in, and valid input/output data is written/read.
Input circuits 2f and 2g receive address status signals /ADSC and /ADSP, respectively. Address status signal /ADSC is supplied from a controller which controls transference of data between the semiconductor memory device used as the secondary cache and a main memory used as the main storage. Signal /ADSP is supplied from a processor using the above semiconductor memory device as the secondary cache. Input circuits 2h-2k receive byte write enable signals /BW1-/BW4. Byte write enable signals /BW1-/BW4 designate enabling of data writing for each byte of one word of 32 bits (4 bytes).
Input circuit 21 receives a main byte write enable signal /MBW which allows writing of data in a unit of byte. When main byte write enable signal /MBW is active, writing of data of a word can be performed in a unit of byte.
Input circuit 2m receives a global write enable signal /GW which enables writing of data for all bytes of one word.
Input circuits 2n-2p receive chip select signals /S1, S2 and /S2, respectively. Chip select signal /S1 is supplied from the processor, and chip select signals S2 and /S2 are supplied from the controller.
Input circuit 2q receives an output enable signal /OE designating a data reading operation. Input circuit 2r receives a flow through mode signal /FT designating a data outputting mode. Flow through signal /FT determines whether the output data is to be output via a register or via the register which is set to the through state.
Internal snooze mode signal /ZZ (in the following description, the internal and external signals are denoted by the same reference characters) sent from input circuit 2c is supplied to all the other input circuits 2a, 2b and 2d-2r. When internal snooze mode signal /ZZ is at the low level of active state, all the internal signals sent via input circuits 2a, 2b and 2d-2r are inactive.
The synchronous semiconductor memory device further includes an internal control signal generating circuit 3 which produces internal control signals in response to the internal signals sent from input circuits 2d-2p and internal clock signal CLK sent from input circuit 2e. The output signals of internal control signal generating circuit 3 are decided in response to rising of internal clock signal CLK. Internal control signal generating circuit 3 includes a gate circuit 3a receiving burst mode advance signal /ADV from input circuit 2d and internal clock signal CLK sent from input circuit 2e. Gate circuit 3a outputs a signal at the high level when internal burst mode advance signal /ADV is at the low level and the internal clock signal CLK is at the high level.
Internal control signal generating circuit 3 further includes an OR circuit 3b which receives internal byte enable signal /BW1 from input circuit 2h and internal main byte enable signal /MBW from input circuit 21, an OR circuit 3c which receives internal byte enable signal /BW2 from input circuit 2iand internal main byte enable signal /MBW, an OR circuit 3d which receives internal byte enable signal /BW3 from input circuit 2j and internal main byte enable signal /MBW, an OR circuit 3e which receives internal byte enable signal /BW4 from input circuit 2k and internal main byte enable signal /MBW, an AND circuit 3f which receives an output signal of OR circuit 3b and internal global write enable signal /GW from input circuit 2m, an AND circuit 3g which receives an output signal of OR circuit 3c and internal global write enable signal /GW, an AND circuit 3h which receives an output signal of OR circuit 3d and internal global write enable signal /GW, an AND circuit 3i which receives an output signal of OR circuit 3e and internal global write enable signal /GW, an NOR circuit 3j which receives internal address status signal /ADSP from input circuit 2g and internal chip select signal /S1 from input circuit 2n, a gate circuit 3k which receives internal address status signal /ADSC from internal circuit 2f and an output signal of NOR circuit 3j, and an AND circuit 31 which receives an output signal of gate circuit 3k and the internal clock signal from input circuit 2e. Gate circuit 3a supplies the burst advance instructing signal to a burst counter 7 which will be described later. An output signal ADSN from AND circuit 3i defines a latch (strobe) timing for the address in this semiconductor memory device, and instructs burst counter 7 to take in least significant two bits A0 and A1 of the latched address.
Internal control signal generating circuit 3 further includes an OR circuit 3m receiving output signals of gate circuit 3j and AND circuit 3f, an OR circuit 3n receiving output signals of gate circuit 3j and AND circuit 3g, an OR circuit 3o receiving output signals of gate circuit 3j and AND circuit 3h, an OR circuit 3p receiving output signals of gate circuit 3j and AND circuit 3i, and a gate circuit 3q receiving internal chip select signals /S1, S2 and /S2 from input circuits 2n, 2o and 2p, respectively. Gate circuit 3q outputs a chip select signal which is active when both internal chip select signals /S1 and /S2 are at the low level and internal chip select signal S2 is at the high level.
OR circuits 3m-3p output the signals which instruct writing of data for corresponding bytes of a 4-byte word. Writing of data of the respective bytes is instructed when internal clock signal CLK is at the high level and respective output signals of OR circuits 3m-3p are at the low level.
The semiconductor memory device further includes an address register 4 which takes in and latches the address signal from input circuit 2a when address strobe (status) signal ADSN from internal control signal generating circuit 3 is active, write registers 5a-5d which take in and latch inverted signals of the output signals of OR circuits 3m-3p included in internal control signal generating circuit 3 in response to rising of internal clock signal CLK, and a chip select register 6 which takes in and latches an internal chip select signal CS in response to activation of address strobe (status) signal ADSN. Write registers 5a-5d output the signals which instruct writing of respective bytes of the 4-byte word. Chip select register 6 outputs the signal CS which enables write/read of data from/to memory cell array 1 of the semiconductor memory device.
Burst counter 7 takes in and outputs address signals A0 and A1 at least significant two bits from address register 4 when address status (strobe) signal ADSN from internal control signal generating circuit 3 is active. Upon each rising of the output signal of gate circuit 3a included in internal control signal generating circuit 3, burst counter 7 changes the taken address signals and outputs the burst address signals A1' and A0'. The manner in which burst counter 7 changes address signals A0 and A1 at the least significant two bits is determined by internal mode designating signal MODE from input circuit 2b. Address signals A0 and A1 may be changed in a linear mode in which the value successively changes by one, or in an interleaved mode in which the value changes in a predetermined order, e.g., of 0-2-1-3. The address signals from address register 4 and address signals A1' and A0 from burst counter 7 are supplied in parallel to row and column decoders which are provided to memory cell array 1.
The semiconductor memory device further includes a write/read control circuit 9 which supplies signals controlling write/read of data in accordance with the output signals of write registers 5a-5d, the output signal of chip select register 6 and internal output enable signal /OE from input circuit 2q, an input/output buffer 10 coupled to data input/output terminals, an input register 11 which takes in and latches write data from input/output buffer 10 in accordance with internal clock signal CLK and the output signal of internal write/read circuit 9, write drivers 12a-12d which write internal write data into selected memory cells in the memory cell array in accordance with the write instructing signal from internal write/read control circuit 9, and an output register 13 which transmits data of the selected memory cells in memory cell array 1 to input/output buffer 10 in accordance with the read instructing signal from internal write/read control circuit 9. Output register 13 operates in accordance with internal flow through signal /FT which is supplied from input circuit 2r, and determines enable/disable of register circuits of output register 13. When internal flow through signal /FT is active, output register 13 holds data for one clock cycle before transmitting the data to input/output buffer 10. When flow through signal /FT is in the inactive state of high level, output register 13 is set to the through state, and immediately transmits the data of a selected memory cell transmitted from memory cell array 1 as received. Internal snooze mode signal /ZZ is also supplied from input circuit 2c to input/output buffer 10.
Internal write/read control circuit 9 includes an AND circuit 9a which receives the output signal of write register 5a and output signal CS of chip select register 5, an AND circuit 9b which receives the output signal of write register 5b and chip select signal CS from chip select register 6, an AND circuit 9c which receives the output signal of write register 5c and chip select signal CS from chip select register 6, an AND circuit 9d which receives the output signal of write register 5d and chip select signal CS from chip select register 6, an OR circuit 9e which receives the output signals of write registers 5a-5d, a gate circuit 9f which receives the chip select signal from chip select register 6 and internal output enable signal /OE from input circuit 2q, and a gate circuit 9g which receives the output signals of OR circuit 9e and gate circuit 9f. The output signals of AND circuits 9a-9d are supplied to write drivers 12a-12d as internal write instructing signals, respectively.
Gate circuit 9f outputs a signal at the high level when chip select signal CS from chip select register 6 is at the high level of the active state and internal output enable signal /OE from input circuit 2q is at the low level. Gate circuit 9g outputs a signal at the high level when the output signal of OR circuit 9e is at the low level and the output signal of gate circuit 9f is at the high level. Therefore, gate circuit 9f outputs a signal at the high level when the semiconductor memory device is set to the selected state and the data output (read) is designated. Gate circuit 9g outputs a signal at the high level when all the data write instructing signals are inactive and the data read or output is designated.
Output register 13 transmits the selected memory cell data from memory cell array 1 to input/output buffer 10 in synchronization with internal clock signal CLK, when the output signal of gate circuit 9g is at the high level. Input register 11 includes register circuits, which are provided corresponding to respective AND circuits 9a-9d, and are activated when AND circuits 9a-9d supply the signals at the high level, respectively. Further, input register 11 takes in the write data from input/output buffer 10 in response to rising of the internal clock signal, and transmits the write data to write drivers 12a-12d corresponding to the activated write instructing signals. Now, operation will be described below with reference to timing charts of FIGS. 2 and 3.
Referring first to FIG. 2, data read operation in the burst mode will be described. At clock cycle 0, address status (strobe) signal /ADSP is set to the low level, and chip select signal /S1 is set to the low level. Also, initial address AD0 is supplied from the processor at cycle 0 (T1 cycle). At clock cycle 1, address status signal ADSN from internal signal generating circuit 3 is set to the high level in response to rising of clock signal CLK, and address register 4 takes in and latches the address signal (initial address AD0) from input circuit 2a. In response to rising of internal address status signal ADSN, burst counter 7 takes in 2-bit address signals A0 and A1 from address register 4 as the initial burst address signals and outputs the same. When data is to be output, all signals /BW1-/BW4, /MBW and /GW for controlling the writing are at the high level, and the write enable signals at the low level are latched into write registers 5a-5d in response to rising of clock signal CLK. Meanwhile, the output signal of gate circuit 3q is set to the high level (signals S2 and /S2 are set to the high and low levels, respectively), the internal chip select signal is set to the high level, and chip select register 6 stores this chip select signal CS at the high level in response to rising of internal address status signal ADSN. In the semiconductor memory device, memory cells in memory cell array 1 are selected in accordance with the address signals sent from address register 4, and the burst counter 7 and data of the selected memory cells are transmitted to output register 13. When flow through signal /FT is at the low level indicating the flow through mode, output register 13 does not hold the data even if internal clock signal CLK is applied thereto, and transmits the data of the memory cells selected in memory cell array 1 to input/output buffer 10 in accordance with the high level signal from gate circuit 9g in internal write/read control circuit 9. Input /output buffer 10 transmits the data supplied from output register 13 to the data input/output terminals in accordance with the read instructing signal (i.e., output signal of gate circuit 9g) from internal write/read control circuit 9.
When flow through signal /FT is at the high level, output register 13 performs the latch operation in accordance with internal clock signal CLK. Specifically, it latches the data of the selected memory cells transmitted from memory cell array 1, and will supply the latched memory cell data to input/output buffer 10 in the next clock cycle 2. Thus, in the flow through mode, data Q0 of the memory cell designated by initial address AD0 is output at the clock cycle (clock cycle 1) immediately subsequent to the cycle (clock cycle 0) in which initial address AD0 is applied. In contrast, when the flow through signal /FT is at the high level indicating the pipeline mode, data Q0 of the memory cell designated by initial address AD0 is output after elapsing of wait cycle T2W of one clock cycle.
In the subsequent clock cycle 1, address status signal /ADSP is maintained at the high level, and burst advance signal /ADV is set to the low level. In this case, the output signal of gate circuit 3a included in internal control signal generating circuit 3 attains the high level in response to rising of clock signal CLK, and the address counter output from burst counter 7 changes. Thereby, the address signal changes in accordance with the sequence designated by the mode signal MODE, and data Q1 of the memory cell at the next address is output. Every time clock signal CLK rises, burst advance signal /ADV is set to the low level and address status signal /ADSP is set to the high level, whereby the addresses are successively designated under the control of burst counter 7, and data Q1-Q3 of the memory cells corresponding to these addresses are read at the respective clock cycles (i.e., clock cycles T2).
In the data write operation, data can be likewise written in the bust mode. In this case, both signals /ADSP and /S1 are set to the low level to set the initial address. At this time, the output signal of gate circuit 3a is set to the high level, the output signals of OR circuits 3m-3p attain the high level, and write registers 5a-5d store inactive write enable signal. Therefore, data writing is not performed in this cycle. In the next clock cycle, address status signal /ADSP is set to the high level, and signals /BW1-BW4, /MBW and /GW for controlling the data writing are set to the intended states, so that, in the following clock cycles, data can be successively written into four addresses starting from the first designated initial address (write data is latched with a delay of one clock cycle, as will be described later).
In the data write operation necessary ones of, write control signals /BW1-/BW4, /MBW and /GW are set to the active state. At this time, signal /ADSP is at the high level, and the output signal of NOR circuit 3a is at the low level. If global write enable signal /GW is at the low level, all the output signals of OR circuits 3m-3p are at the low level, and write registers 5a-5d take in and latch the active write enable signals at the high level in response to rising of clock signal CLK. All the output signals of AND circuits 9a-9d attain the high level, all write drivers 12a-12d are activated, and data of 32 bits (i.e., data of one word) supplied from input register 11 is written into the selected memory cells in memory cell array 1. The output signal of gate circuit 9g is at the low level because the output signal of OR circuit 9e is at the high level, output register 13 is inactive, and input/output buffer 10 is set to the data writing state. At this time, burst advance signal /ADV is set to the low level at the rising of clock signal CLK, as is done in the read operation, whereby addresses are successively designated under the control of burst mode counter 7, and data can be written into the memory cells corresponding to the internally designated addresses.
FIG. 3 is a timing chart showing the data write operation. As shown in FIG. 3, address AD0 taken in at write cycle 1 is stored in address register 4 in this cycle 1, and write data D (AD0) taken in at cycle 2 is stored in input register 11. When data write is designated in cycle 2, the data stored in input register 11 is written into the memory cells designated by the address stored in address register 4. Data D (AD1) supplied in clock cycle 3 is written into the memory cells at address AD1 which was taken in at clock cycle 2. When data read is designated in clock cycle 3, data Q (AD2) of the memory cells corresponding to address AD2 are read in the subsequent clock cycle 4 (in the case of pipeline output mode).
When flow through signal /FT is set to the high level and the data read is performed in the pipeline mode, access to the initial address requires a wait cycle T2W of one clock cycle. However, the access time with respect to clock signal CLK is determined by only the delay time of the output portion included in input/output buffer 10. Therefore, fast clock access (i.e., access relative to the clock) can be achieved. In the burst read cycle (T2), the wait cycle is not required. Therefore, data can be read fast. As compared with the case where flow through signal /FT is at the low level of active .state and data read is performed in the flow through mode, data reading in this burst mode (pipeline mode) requires the wait cycle Taw, so that data transmission efficiency thereof is relatively low. However, such an advantage can be achieved that even a semiconductor memory device of a relatively low operation speed can achieve the fast clock access (for fast operation, an expensive BiCMOS process must be employed).
FIG. 4 is specifically shows a structure of the input circuit shown in FIG. 1. In FIG. 4, address status signals /ADSC and /ADSP are represented by one address status (strobe) signal /ADS. Likewise, write enable signals /BW1-/BW4, /MBM and /GW are represented by one write enable signal /WEN. The input circuits for signals MODE and /FT are not shown in FIG. 4. These signals are directly applied to burst counter and input/output register via the input circuit as shown in FIG. 1. Input circuits 2b and 2r for these signals MODE and /FT are supplied with internal snooze mode signal ZZ from input circuit 2c receiving external snooze mode signal /ZZ.
Input circuit 2c is formed of an inverter IV1 receiving snooze mode signal /ZZ externally supplied via an input terminal 30a. Input circuit 2e receives external clock signal CLK applied via an input terminal 30b and internal snooze mode signal ZZ from input circuit 2c, and produces the internal clock signal INT.CLK. An input circuit 20a receives address status signal /ADS via an input terminal 30c, and also receives internal snooze mode signal ZZ. An input circuit 20b receives write enable signal /WEN via an input terminal 30d, and also receives internal snooze mode signal ZZ. Input circuit 2a receives the address signal via an input terminal 30e, and also receives internal snooze mode signal ZZ. An input circuit 20c receives input data DQ(D) via an input terminal 30f, and also receives internal snooze mode signal ZZ. Input circuit 2g receives output enable signal /OE via an input terminal 30g, and also receives internal snooze mode signal ZZ.
Each of input circuits 2a, 2e, 2g and 20a-20c is formed of an NAND gate NR receiving internal snooze mode signal ZZ and the signal from the corresponding input terminal, and an inverter IV2 receiving the output signal of NAND gate NR.
The output signals of input circuits 2e, 20a, 20b, 20c and 2g are supplied to internal circuits 35a-35f, respectively. Internal circuits 35a-35f correspond to the input circuits included in the input/output buffer and the internal control signal generating circuit shown in FIG. 1. For example, internal circuit 35a corresponds to gate circuit 3a and write registers 5a-5d. Internal circuit 35b corresponds to NOR circuit 3j and gate circuits 3k and 31 in FIG. 1. Internal circuit 35c corresponds to, for example, OR circuits 3b-3e and AND circuits 3f-3i. Internal circuit 35d corresponds to address register 4. Internal circuit 35e corresponds to the input buffer included in input/output buffer 10 in FIG. 1. Internal circuit 35f corresponds to gate circuit 9f in internal write/read control circuit 9 shown in FIG. 1.
When the processing stops and it is determined that an external access to the semiconductor memory device is not necessary, the processor sets the external snooze mode signal /ZZ to the high level. When only holding of data in a DRAM (Dynamic Random Access Memory) which is a main storage is to be performed in a battery-powered personal computer for example, snooze mode signal /ZZ is set to the high level of active state. In this case, as shown in FIG. 5, external snooze mode signal (EXT.) /ZZ is supplied asynchronously to external clock signal EXT.CLK. Internal snooze mode signal (INT.)ZZ is set to the low level of active state after elapsing of a delay time of inverter IV1. When internal snooze mode signal (INT.)ZZ is set to the low level, output signals of input circuits 2e, 2a and 20c are fixed to the low level. Therefore, charging and discharging are not performed in input circuits 2e, 20a-20c, 2a and 2q, so that power consumption can be reduced. In this case, the internal signal at the low level of active state may be supplied to the internal circuits. Even in this case, each external control signal is latched by the register in response to rising of internal clock signal INT.CLK as shown in FIG. 1, so that internal operation of the semiconductor memory device is inhibited due to stop of generation of internal clock signal INT.CLK.
However, snooze mode signal /ZZ is supplied asynchronously to external clock signal EXT.CLK (CLK). Therefore, when external snooze mode signal (EXT.)ZZ is set to the high level at substantially same timing as rising timing of external clock signal (EXT.)CLK, for example, as shown in FIG. 6, the following problem arises.
Input circuit 2c is formed of inverter IV1, and has a delay time of, e.g., several nanoseconds. As shown in FIG. 6, therefore, when external snooze mode signal EXT./ZZ is set to the high level at the same timing as rising timing of external clock signal EXT.CLK, internal clock signal INT.ZZ attains the low level after elapsing of delay time Td of input circuit 2c. For example, in clock input circuit 2e, delay by Td therefore occurs in the timing of cutting off external clock signal EXT.CLK applied to input terminal 30b. Consequently, external clock signal EXT.CLK which is applied during delay time Td passes through input circuit 2e, and internal clock signal INT.CLK attains the high level for that period. Operation similar to the above is performed in the other input circuits. Therefore, when write enable signal /WEN is set to the low level in this state, the input register operates in accordance with internal clock signal INT.CLK, and internal chip select signal (INT.)CS attains the high level. Also, the address signal is latched by the register, and data is written into a memory cell in accordance with the erroneously latched address signal. This results in a problem that the memory cell data to be stored is destroyed.
In particular, if all the input circuits have the same common structure as shown in FIG. 4, the internal signals may be held at the active state during the snooze mode, which increases the possibility that malfunction, particularly, writing of erroneous data is performed due to internal clock signal INT.CLK generated in a spike-like form.
In the synchronous semiconductor memory device, the external signals are taken in at rising of internal clock signal INT.CLK, and its internal operation is determined depending on the states of taken signals. Therefore, if a similar problem occurs also at another input circuit, malfunction of a circuit may occur due to generation of an unexpected internal signal in this synchronous semiconductor memory device.
If external snooze mode signal EXT.ZZ is lowered at substantially the same timing as the rising timing of external clock signal EXT.CLK in order to terminate the snooze mode operation, this results in generation of internal clock signal INT.CLK, so that a similar problem arises.
In order to avoid the above problems, it is necessary to deactivate all the external control signals upon entering of the snooze mode. For example, upon entering of the snooze mode, it is necessary to deactivate signal /WEN and all chip select signals CS (S2, /S2, /S1) and set address status signal /ADS to the high level in order to prevent the setting of the data write state. Therefore, whenever the memory device enters or exits the snooze mode, an external processing unit must set the states of not only snooze mode signal EXT./ZZ but also other signals, resulting in a problem that a load to the external processing unit increases when entering the snooze mode.